
cassys timing:

1757, 4377, 945, 945, 883, 1767, sync = 0



- all versions of CPC speedlock have a clicking header composed from a sequence of pulses.

version 1 (eidolon, bmx freestyle): 1e, 22, 24, 26
version 1b (tarzan): 18, 1e, 1c, 20
version 5 (hudson hawk): 1e, 2a, 28, 22

tarzan appears to be first to use type 2 data format which has sub-blocks.
each sub-block has a 24 (3*7) pulse block between each data block.

it has x initial blocks, followed by sub-blocks.


- followed by 5 bits of data at a different speed (data is always checked with $1d)

- all except type 1 have 21 pulses between the sub-blocks (3 * 7 pulses. The middle 7 pulses must all be 1) - these pulses are always at the same speed 
for all speedlock versions

- the data for speedlock v1 is not protected
e.g.
ld (ix+0),a
- speedlock's later than v1 are protected 

using the following code:

ld a,prot_byte1
xor l
add a,prot_byte2
ld (ix+0),a


- speedlock's later than v2 are comprised of sub-blocks.
- a table is used to define where each block will be located
table information:
2 bytes location
2 bytes	length
1 byte flag






