## Interrupts in the CPC

In the CPC the Gate Array generates maskable interrupts, to do this it uses the HSYNC and VSYNC signals from the CRTC, a 6-bit internal counter and monitors the interrupt acknowledge from the Z80.

The 6-bit counter is incremented after each HSYNC from the CRTC. (When standard CRTC display settings are used, this is equivalent to counting scan-lines). (to be confirmed: does gate array count positive or negative edge transitions of HSYNC signal?)

When the counter equals "52", it is cleared to "0" and the Gate-Array will issue a interrupt request to the Z80, the interrupt request remains active until the Z80 acknowledges it. These two operations will continue even if the interrupt has not been acknowledged. (When standard CRTC display settings are used, this has the potential to generate a interrupt every 52 scan-lines giving 6 possible interrupts per video frame).

The Z80 will acknowledge if the interrupt acknowledge is enabled. (Z80 internal flag IFF1="1"; this flag can be set with the EI instruction). (When the Z80 acknowledges a interrupt /IORQ = "0" and /M1 = "0" from the Z80.) If IFF1="0" interrupts are ignored and there is no acknowledge.

When the interrupt is acknowledged, this is sensed by the Gate-Array. The top bit (bit 5), of the counter is set to "0" and the interrupt request is cleared. This prevents the next interrupt from occuring closer than 32 HSYNCs time.

If bit 4 of the "Select screen mode and rom configuration" register of the Gate-Array (bit 7="1" and bit 6="0") is set to "1" then the interrupt request is cleared and the 6-bit counter is reset to "0".

The Gate-Array senses the VSYNC signal. If two HSYNCs have been detected following the start of the VSYNC then there are two possible actions:

1. If the top bit of the 6-bit counter is set to "1" (i.e. the counter >=32), then there is no interrupt request, and the 6-bit counter is reset to "0". (If a interrupt was requested and acknowledged it would be closer than 32 HSYNCs compared to the position of the previous interrupt).
2. If the top bit of the 6-bit counter is set to "0" (i.e. the counter <32), then a interrupt request is issued, and the 6-bit counter is reset to "0".

In both cases the following interrupt requests are synchronised with the VSYNC.

Interrupts generated by the Gate-Array are the only source of interrupts in the CPC system unless they are generated by expansion devices.

The NMI interrupt of the Z80 is not used by the Amstrad CPC hardware but is available for expansion devices to use.

## Interrupts in the CPC+

The CPC style interrupts as described above are available in two cases:

- The ASIC is "locked",
- The ASIC is "un-locked" and the Programmable Raster interrupt (PRI) is set to "0".

CPC style interrupts and Programmable Raster interrupts cannot be active at the same time. If the Programmable Raster Interrupt (PRI) is active (it is not equal to "0") then interrupt requests will not be generated by the CPC style interrupts. However, the 6-bit counter will continue to operate as above.

If a Programmable Raster Interrupt is acknowledged, then the top-bit (bit 5) of the Gate Array 6-bit counter is reset. If CPC interrupts were reactivated, this forces the next interrupt to not be closer than 32 lines.

The following interrupts are available:

- The CPC style interrupts described here,
- Programmable Raster Interrupt,
- Interrupt from DMA channel 0,
- Interrupt from DMA channel 1,
- Interrupt from DMA channel 2.

The CPC+ supports Z80 Interrupt mode 2 (activated with "IM 2" instruction), and provides a interrupt vector based on the source of the interrupt. See the datasheet for the CPC+ ASIC for more information.

## Interrupts in the KC compact system

The interrupts are generated by the Z8536 CIO chip using Counter Timer 3. The Counter/Timer output is connected to the interrupt request generation. The Counter/Timer input is connected to HSYNC. The Counter/Timer trigger input is connected to a signal which is generated when 2 HSYNCs have been detected after the start of the VSYNC. The Counter/Timer Gate input is connected to 5V.

Under normal settings the CIO is programmed to count HSYNC transitions. Each transition will decrement the count for Counter Timer 3. When the count reaches zero, terminal count is signalled through the Counter/Timer output. This will cause a interrupt request to be generated.

The VSYNC signal is used to start the counter and to reset it to it's initial count, this enables interrupts to be synchronised with the VSYNC.

The counter is configured to restart when terminal count has been reached, and this means that the CIO will generate a interrupt request every 52 HSYNCs.

However the CIO is a sophisticated counter and timer chip. It could be configured to count any number of HSYNCs, allowing interrupts every-line, or count from it's internal clock allowing multiple interrupts per line. There are many more possibilities, and the KC compact therefore has a much more flexible interrupt system.

Regardless of the CIO settings, the interrupt request is cleared by the Z80 acknowledging the request or by writing a "1" to bit 4 of the the "Select screen mode and rom configuration" register of the Gate-Array (bit 7="1" and bit 6="0").

The interrupt acknowledge from the Z80 does not affect the CIO counter and interrupts may occur closer than 32 lines.