

SCSI-16 Module Tests

    The SCSI-16 Module Tests menu contains tests that exercise, verify the
functionality of the SCSI-16 daughter board. Its contains 12 groups of tests.

    Following is the SCSI-16 Tests top-level menu.

	Host Bus Logic Tests/
	Local Bus Logic Tests/
	Ethernet Tests/
	Host-Local Bus Access Dual-Port RAM Tests/
	SCSI Processor 1 Tests/
	SCSI Processor 2 Tests/
	DMA Bypass Tests/
	DMA Controller Tests/
	SCSI Proc 1 DMA Bypass Cache Coherency Tests/
	SCSI Proc 2 DMA Bypass Cache Coherency Tests/
	SCSI Proc 1 DMA Cache Coherency Tests/
	SCSI Proc 2 DMA Cache Coherency Tests/

Host Bus Logic Tests

The Host Bus Logic Test group contains tests to verify that the host
can access the daughter card properly via the expansion bus. The
description for each test is described below:

    Host Bus Access Dual-Port RAM Data Line Test
	This test writes a walking one pattern to location 0 (0x80800000) of
	the Dual-port RAM to verify the integrity of the 32 bit data line.

    Control Register Test
	Verify several bits in this register can be set or clear as they were
	selected. This test writes each register with various patterns,  reads
	the register under test after doing a write, and checks that the data
	read back is correct.

    Interrupt Mask Register Test
	This test verifies that the Interrupt/mask register of the SCSI-16
	board can hold data correctly.    This test writes each register with
	various patterns,  reads the register under test after doing a write,
	and checks that the data read back is correct.

    Diagnostic Control Register Test
	This test verifies that the Diagnostic Control  register of the SCSI-16
	board can hold data correctly.    This test writes each register with
	various patterns,  reads the register under test after doing a write,
	and checks that the data read back is correct.

    Performance Counter Test
	This test tests the Xilinx-based performance counter. It tests the
	device as a dedicated counter, assuming it's already been initialized
	with the appropriate vectors. The 32-bit counters count at 50 MHz
	whenever certain parts of the logic control the local node bus. These
	six parts are:

	       o    The Ethernet channel.
	       o    The SCSI Processor 1, accessing the node.
	       o    The SCSI Processor 2, accessing the controller.
	       o    The Local Bus Idle time.
	       o    Node utilization of Daughter board.
	       o    Daughter board utilization of Node bus.

	For each counter, the test increments a diagnostic clock source and
	verifies that the counter contain the expected count after each clock.
	The test then takes the counter under test out of its diagnostic mode,
	so it behaves like a normal 32-bit counter. One last clock verifies
	that the counter value rolls over to zero.

    82510 Serial Interface Initialization Test
	This test verify the 82510 can be initialize and wake up with a good
	status.

    82510 Serial Interface Internal Loopback Test
	This test checks the UART functionality on the SCSI-16 daughter card.
	The UART  is an Intel 82510 serial controller. The test puts the
	controller into internal loopback mode which causes the contents of the
	transmit FIFO of the chip to be received immediately by the receive
	FIFO. The data received is compared with the data sent.

    82510 Serial Interface External Loopback Test
	This test checks the serial port functionality on the SCSI-16 daughter
	card. The UART  functionality had been tested in the internal loopback
	test, this test required an external loopback connector to run with the
	test. The loopback connector route the data from the transmit line back
	to the receive line which causes the contents  of the transmit data to
	be received immediately. The data received  is compared with the data
	sent.

    82510 Serial Interface Interrupt Test
	This test verify the 82510 can assert the interrupt signal back to the
	diagnostic control register. The sequence of test described below:

	Clear the expansion interrupt mask bit in DP status low  so no
	expansion board interrupt gets through to the node. Set the SERINT bit
	in the SCSI16 interrupt mask register to prevent a serial interrupt
	from leaving the SCSI16 board. Initialize the serial interface chip.
	Read the SCSI16 interrupt status register and verify that the SERINT
	bit is not set; if it is, display an error and fail the test

	Put the serial interface in loopback mode. Force an overrun error
	by writing characters to the transmit port until an overrun error
	is posted in the 82510's receive status register. Check that the
	SERINT bit in the SCSI16 interrupt status register is set,
	indicating the 82510 generated an interrupt.  Re-initialize the
	82510 and clear the receive and transmit FIFOs.

    Daughter Card Interrupt Test
	This test verify the interrupt from the daughter card can propagate
	back the baseboard. It use the serial interface to generate the
	interrupt source. When the interrupt occurs, it checks that the EXPINT
	bit in DP status low is set, indicating that clearing the mask bit
	allowed the serial interrupt to be propagated to the node board.
	Re-initialize the 82510 and clear the receive and transmit FIFOs. Check
	that the SERINT bit in the SCSI16 interrupt status register is now
	clear. Check that the EXPINT bit in DP status low is clear to verify
	that the interrupt was cleared on the node board

    Byte Lane 0-7 Parity Test
	This test check the parity bit (PARINT) is reflect the change when
	force the interrupt on each byte lane. The combination byte pattern
	used to check the Host Bus parity generation. Some patterns are written
	with the force parity mode set to PAR_TEST_CHECKER to check the ninth
	bit of the octal parity generator/checker. This will initiate a parity
	interrupt.  The absence/presence of the parity interrupt is checked in
	the Interrupt Status Register along with the byte lane affected in the
	Status Register.

    Parity Error Interrupt Test
	This test verify the parity error interrupt from the daughter card can
	propagate back the baseboard. It force the parity similar in the Byte
	Lane Parity test. When the interrupt occurs, it checks that the EXPINT
	bit in DP status low is set, indicating that clearing the mask bit
	allowed the parity interrupt to be propagated to the node board.  
	Write a byte lane number to PSEL2-0 in Diagnostic Control
	Register then check that the PARINT bit in the SCSI16 interrupt
	status register is now clear. Check that the EXPINT bit in DP
	status low is clear to verify that the interrupt was cleared on
	the node board

    Host Bus Access Dual-Port RAM Cell Addressing Test
	This test writes an unique pattern at each diagonal address and
	read back to check for the integrity of the address lines.

    Host Bus Access Dual-Port RAM Cell Integrity Test
	This test checks the ability of each Dual-port RAM cell to hold
	data correctly when accessing from the baseboard.  The test
	does this by writing various data patterns to each memory
	location and then reading the data back and verifying that it
	is correct.  The test uses data patterns of 5's, A's, 0's, F's.

    Host Bus Access Dual-Port RAM Byte Access Test
	This test writes all of memory from 0x80800000 to the top of
	memory by bytes and then reads each byte and checks that it
	contains the correct data. The data written to the bytes is an
	incrementing pattern starting at 0x0 and going to 0xff before
	starting over at 0x0 again. Therefore, byte address 0x80800000
	is written with 0x0, 0x80800001 with 0x1, 0x808000ff is written
	with 0xff, 0x80800100 is written with 0x0, etc.

    Host Bus Access Dual-Port RAM Uniqueness Test
	This test writes an unique pattern at each diagonal address and read 
	back to check for the integrity of the address lines Test


Local Bus Logic Tests

This test group contains tests to ensure the integrity of the SCSI-16
daughter card local bus.  The target is the Local RAM, EPROM and the
Dual-port RAM. The description for each test is described below:

    Local RAM Data Line Test
	This test writes a walking one pattern to location 0
	(0x80700000) of the Local RAM to verify the integrity of the 32
	bit data line.

    Local RAM Addressing Test
	This test writes an unique pattern at each diagonal address and
	read back to check for the integrity of the address lines.

    Local RAM Cell Integrity Test 
	This test checks the ability of each Local RAM cell to hold
	data correctly.  The test does this by writing various data
	patterns to each memory location and then reading the data back
	and verifying that it is correct.  The test uses data patterns
	of 5's, A's, 0's, F's.

    Local RAM Byte Access Test
	This test writes all of memory from 0x80700000 to the top of
	memory by bytes and then reads each byte and checks that it
	contains the correct data. The data written to the bytes is an
	incrementing pattern starting at 0x0 and going to 0xff before
	starting over at 0x0 again. Therefore, byte address 0x80700000
	is written with 0x0, 0x80700001 with 0x1, 0x807000ff is written
	with 0xff,  0x80700100 is written with 0x0, etc.

    Local RAM Uniqueness Test
	This test writes to each 32 bit location in Local RAM with an
	unique pattern (increment pattern starts from 0) and read back
	for comparison to verify if the address and data are unique.

    Flash EPROM Checksum Test
	This test accumulates a 16-bit of the flash prom from 0
	(0x8ff00000) to 0x3fff8 (0x8ff3fff8). This sum is identical to
	the 2 bytes sum stored at location 0x3fffE (0x8ff3fffE) and
	0x3ffff (0x8ff3ffff) when it was built.

    Local Bus Access Dual-Port RAM Data Line Test
	This test writes a walking one pattern to location 0
	(0x80900000) of the Dual-port RAM access from the daughter card
	side to verify the integrity of the 32 bit data line.

    Local Bus Access Dual-Port RAM Addressing Test
	This test writes an unique pattern at each diagonal address and
	read back to check for the integrity of the address lines.

    Local Bus Access Dual-Port RAM Cell Integrity Test
	This test checks the ability of each Dual-port RAM cell to hold
	data correctly.  The test does this by writing various data
	patterns to each memory location and then reading the data back
	and verifying that it is correct.  The test uses data patterns
	of 5's, A's, 0's, F's.

    Local Bus Access Dual-Port RAM Byte Access Test
	This test writes all of memory from 0x80900000 to the top of
	memory by bytes and then reads each byte and checks that it
	contains the correct data. The data written to the bytes is an
	incrementing pattern starting at 0x0 and going to 0xff before
	starting over at 0x0 again. Therefore, byte address 0x80900000
	is written with 0x0, 0x80900001 with 0x1, 0x809000ff is written
	with 0xff, 0x80900100 is written with 0x0, etc.

    Local Bus Access Dual-Port RAM Uniqueness Test
	This test writes to each 32 bit location in the Dual-port RAM
	with an unique pattern (increment pattern starts from 0) and
	read back for comparison to verify if the address and data are
	unique.

Ethernet Tests

The ethernet tests check the operation of the 82596 for 32 bit linear
mode of operation. The basic algorithm used in all tests except the
first four is:

    -  Configure and Initialize the 82596 data structures.
    -  Reset the 82596.
    -  Set the 82596 SCP to the preconfigured data structure area.
    -  Clear Interrupts.
    -  Issue a CU start command.
    -  Delay 10 miliseconds and check command completion.
    -  If CU started then start the RU and the CU (which starts test commands).
    -  Check All commands issued for correct completion.
    -  Check transferred data for correctness.

The first four tests algorithms are very simple and are detailed in
their description sections below. The special specifics for each test
is detailed in the following sections.

    82596 LAN Co-processor Self Test
	This test issues a chip self test command to the 82596.  The
	chip test results are placed in local ram 0x80700000 and if not
	zero an error is reported.

    82596 LAN Co-processor Reset Test
	This test checks to see that the 82596 can come out of chip
	reset properly and configure the SCP data structure address.
	The SCB status is checked and if it has Completion and OK
	status this test passes.

    Ethernet Command Unit Test
	This test checks the Command Unit (CU) for operation.  The test
	resets the chip as in the reset test and then issues a CU Start
	command which tells the 82596 to do a configure and a No-Op
	(NOP) command.  The status is checked in the SCB, the configure
	command block and the NOP command block. If it has Completion
	and OK status this test passes.

    Ethernet Receive Unit Test
	This test checks the Receive Unit (RU) for operation.  The test
	resets the chip as in the reset test and then issues a CU Start
	command which tells the 82596 to do a configure and a No-Op
	(NOP) command.  The status is checked in the SCB, the configure
	command block and the NOP command block.  The test then issues
	an RU Start command.  The Receive unit RFD status is checked to
	ensure a busy status indicating that the receiver has started
	properly (in loopback mode).  If the CU commands have
	Completion and OK status this test passes.

    82596 LAN Co-processor Diagnose Test
	A DIAGNOSE command is issued to the 82596. The status of this
	command is checked to ensure proper completion.

    82596 LAN Co-processor Loopback Test
	The 82596 is placed in internal loopback mode and a 1984 byte
	packet is transmitted from local ram back into local ram. The
	data is checked.

    82503 Transceiver Loopback Test
	The 82596 is placed in external loopback mode and a 1984 byte
	packet is transmitted from local ram through the 82503 and back
	through the 82596 which then puts the data back into local ram.
	The data is checked.

    Ethernet Memory Addressing Test
	The 82596 is placed in external loopback mode and a 1664 byte
	packet is transmitted from local ram back into local ram just
	like the 82503 transceiver test. The difference is that the
	receive buffer descriptors point to 128 byte memory segments
	which are aligned on an increasing power of two address
	boundary (0, 128, 256, 512, 1024, 2048... ).

    Ethernet Interrupt Test
	The 82596 is placed in internal loopback mode. Two 520 byte
	packets are transmitted from local ram back into local ram.
	Interrupts are enabled and the appropriate traps are taken. The
	trap handler checked to ensure that LANINT and DINT2 are set in
	the SCSI16 interrupt status register. If  the test does not
	receive two interrupts from the transmitted packets an error is
	reported.

    Ethernet CRC Test
	The 82596 is placed in internal loop back mode. CRC insertion
	is disabled from the transmit packet and a 128 byte packet is
	transmitted. If the packet is received without a CRC error
	detected in the RFD status an error is reported.

    Ethernet External Loopback Test
	This test is normally not run and requires the board's loopback
	jumper to be installed for proper test operation. This test
	places the 82596 in normal operational mode. A transmit command
	with 256 bytes of data are transmitted to itself (via
	destination ethernet address from the X24C02 serial ROM).

	After the transmit command has completed a TDR command is then
	issued and the TDR completion status is reported to allow the
	user to evaluate line conditions (See 32-Bit Local Area
	Network (LAN) Component User's Manual 1992 for a detailed
	description of the TDR command (296853-001).

    X24C02 Serial Rom Read Test
	This test will read eight bytes from the X24C02 serial ROM. If
	the ethernet address fails to be an Intel Corporation allotted
	address the test will fail.


Host-Local Bus Access Dual-Port RAM Tests

This test group insures the integrity of the SCSI-16 daughter card
Dual-port RAM when accessing from both side of the RAM.

    Dual Access Dual-Port RAM Data Line Test
	This test writes a walking one pattern to location 0
	(0x80800000) then access  from the node  using address
	0x80900000 of the Dual-port RAM to verify the integrity of the
	32 bit data line of the Dual-port from both side.

    Dual Access Dual-Port RAM Cell Addressing Test
	This test writes an unique pattern at each diagonal address and
	read back from other side to check for the integrity of the
	address lines.

    Dual Access Dual-Port RAM Cell Integrity Test
	This test checks the ability of each Dual-port RAM cell to hold
	data  correctly when reading and writing from both side.  The
	test does this by writing various data patterns to each memory
	location and then reading the data back and verifying  that it
	is correct.  The test uses data patterns of 5's, A's, 0's,
	F's.  This test checks all of memory location in the Dual-port RAM.

    Dual Access Dual-Port RAM Byte Access Test
	This test writes all of memory from 0x80700000 to the top of
	memory by bytes . The data written to the bytes is an
	incrementing pattern starting at 0x0 and going to 0xff before
	starting over at 0x0 again. Therefore, byte address 0x80700000
	is written with 0x0, 0x80700001 with 0x1, 0x807000ff is written
	with 0xff, 0x80700100 is written with 0x0, etc. When reading
	back for comparison the address 0x80900000 is used to access
	from the other side of the Dual-port RAM.

    Dual Access Dual-Port RAM Uniqueness Test
	This test writes to each 32 bit location in Dual-port RAM with
	an unique pattern (increment pattern starts from 0) and read
	back from the other size for comparison to verify if the
	address and data are unique.

SCSI Processor 1 Tests

The SCSI Processor 1 Tests verify the functionality of the SCSI
Processor 2 and its interface with the various expansion board RAM's
and Node RAM.  Following is the SCSI Processor 1 Tests menu.

	Processor 1 Alive Test
	Processor 1 Data Path Test
	Processor 1 Register-Register Test
	Processor 1 Interrupt Test
	Processor 1 Register-Local RAM Test
	Processor 1 Local RAM-Register Test
	Processor 1 Local RAM-Local RAM Test
	Processor 1 Local RAM-Dual Port RAM Test
	Processor 1 Dual Port RAM-Local RAM Test
	Processor 1 Local RAM-Node RAM Test
	Processor 1 Node RAM-Local RAM Test
	Processor 1 Select Test
	Processor 1 Select w/ATN Test
	Processor 1 Command Descriptor Block Test
	Processor 1 Read Data Test
	Processor 1 Write Data Test

    Processor 1 Alive Test
	The Processor 1 Alive Test verifies that the processor is
	present and able to be read. The processor is released from
	reset and initialized to return external readys and proper
	parity. The SCSI Control Zero register is then read for an
	expected pattern of 0xc0.

    Processor 1 Data Path Test
	The Processor 1 Data Path Test verifies the data lines to SCSI
	Processor 1. Patterns 0x00000000, 0x0000ffff, 0x00ff00ff,
	0x0f0f0f0f, 0x33333333, 0x55555555, and 0xffffffff are written
	to the processor Scratch Register A, read, and verified.

    Processor 1 Register-Register Test
	The Processor 1 Register-Register Test verifies that the
	processor can be initialized and run a simple script located in
	Local RAM that transfers 4 bytes from processor Scratch
	Register A to Scratch Register B.  A pattern of 0x01020304 is
	written into processor Scratch Register A. The processor DMA
	Scripts Pointer Register is written with  the address of the
	script in Local RAM forcing the processor to start executing
	the script. The processor Scratch Register B is read and the
	data verified.

    Processor 1 Interrupt Test
	The Processor 1 Interrupt Test verifies the SINT0 interrupt bit
	in the SCSI-16 Interrupt Status Register. The bit is checked
	for clear, the bit is checked for set after a small SCSI
	transfer, and the bit is checked for clear after writing the
	SCSI-16 Interrupt Status Register.

    Processor 1 Register-Local RAM Test
	The Processor 1 Register-Local RAM Test verifies that the
	processor can transfer 4 bytes from processor Scratch Register
	A to Local RAM.  A pattern of 0x01020304 is written into
	processor Scratch Register A. The processor transfers the 4
	bytes to a location in Local RAM. The data is read and
	verified.

    Processor 1 Local RAM-Register Test
	The Processor 1 Local RAM-Register Test verifies that the
	processor can transfer 4 bytes from a location in Local RAM to
	processor Scratch Register A.  A pattern of 0x01020304 is
	written into the location in Local RAM.  The processor
	transfers the 4 bytes to Scratch Register A. The data is read
	and verified.

    Processor 1 Local RAM-Local RAM Test
	The Processor 1 Local RAM-Local RAM Test verifies that the
	processor can transfer 64K bytes from a location in Local RAM
	to another location in Local RAM.  An incrementing byte pattern
	is written to one location in Local RAM. The processor
	transfers the 64K bytes to another location in Local RAM. The
	date is read and verified.

    Processor 1 Local RAM-Dual Port RAM Test
	The Processor 1 Local RAM-Dual Port RAM Test verifies that the
	processor can transfer 26K bytes from a location in Local RAM
	to a location in Dual Port RAM.  An incrementing byte pattern
	is written to the location in Local RAM. The processor
	transfers the 26K bytes to Dual Port RAM. The date is read and
	verified.

    Processor 1 Dual Port RAM-Local RAM Test
	The Processor 1 Dual Port RAM-Local RAM Test verifies that the
	processor can transfer 26K bytes from a location in Dual Port
	RAM to a location in Local RAM.  An incrementing byte pattern
	is written to the location in Dual Port RAM. The processor
	transfers the 26K bytes to Local RAM. The date is read and
	verified.

    Processor 1 Local RAM-Node RAM Test
	The Processor 1 Local RAM-Node RAM Test verifies that the
	processor can transfer 64K bytes from a location in Local RAM
	to a non-cached location in Node RAM.  An incrementing byte
	pattern is written to the location in Local RAM. The processor
	transfers the 64K bytes to Node RAM. The date is read and
	verified.

    Processor 1 Node RAM-Local RAM Test
	The Processor 1 Local RAM-Node RAM Test verifies that the
	processor can transfer 64K bytes from a non-cached location in
	Node RAM to a location in Local RAM.  An incrementing byte
	pattern is written to the location in Node RAM. The processor
	transfers the 64K bytes to Local RAM. The date is read and
	verified.

    Processor 1 Select Test
	The Processor 1 Select Test verifies that the processor can
	accomplish a SELECT sequence. The processor is put in loopback
	mode. The processor DMA Scripts Pointer Register is written
	with  the address of the script in Local RAM forcing the
	processor to start executing the SELECT script. When SEL goes
	high and BSY goes low, BSY is asserted by writing the processor
	Output Control Latch Register. The processor SCSI Bus Control
	Lines Register is read to verify that SEL went low.

    Processor 1 Select w/ATN Test
	The Processor 1 Select w/ATN Test verifies that the processor
	can accomplish a SELECT w/ATN sequence. The processor is put in
	loopback mode. After the processor has been Selected, the
	Output Control Latch Register is written with REQ, BSY, and MSG
	OUT. The processor Bus Data Lines Register is read to verify
	the proper MSG OUT.

    Processor 1 Command Descriptor Block Test
	The Processor 1 Command Descriptor Block Test verifies that the
	processor can accomplish a CDB sequence. The processor is put
	in loopback mode. A 6 byte pattern of 0x12, 0x34, 0x56, 0x78,
	0xab, and 0xcd is written to the processor. The processor Bus
	Data Lines Register is read to verify the pattern.

    Processor 1 Read Data Test
	The Processor 1 Read Data Test verifies that the processor can
	accomplish a DATA_IN sequence. The processor is put in loopback
	mode. A 5 byte pattern of 0x01, 0x02, 0x03, 0x04, and 0x05 is
	written to the processor Output Data Latch Register. The
	processor transfers the bytes to a buffer in Node RAM. The data
	is verified.

    Processor 1 Write Data Test
	The Processor 1 Write Data Test verifies that the processor can
	accomplish a DATA_OUT sequence. The processor is put in
	loopback mode. A 5 byte pattern of 0x01, 0x02, 0x03, 0x04, and
	0x05 is put in a buffer in Node RAM. The processor starts
	executing and the data is read from Node RAM into the
	processor. The processor Bus Data Lines Register is read and
	the data verified.


SCSI Processor 2 Tests

The SCSI Processor 2 Tests verify the functionality of the SCSI
Processor 2 and its interface with the various expansion board RAM's
and Node RAM.  Following is the SCSI Processor 2 Tests menu.

	Processor 2 Alive Test
	Processor 2 Data Path Test
	Processor 2 Register-Register Test
	Processor 2 Interrupt Test
	Processor 2 Register-Local RAM Test
	Processor 2 Local RAM-Register Test
	Processor 2 Local RAM-Local RAM Test
	Processor 2 Local RAM-Dual Port RAM Test
	Processor 2 Dual Port RAM-Local RAM Test
	Processor 2 Local RAM-Node RAM Test
	Processor 2 Node RAM-Local RAM Test
	Processor 2 Select Test
	Processor 2 Select w/ATN Test
	Processor 2 Command Descriptor Block Test
	Processor 2 Read Data Test
	Processor 2 Write Data Test

    Processor 2 Alive Test
	The Processor 2 Alive Test verifies that the processor is
	present and able to be read. The processor is released from
	reset and initialized to return external readys and proper
	parity. The SCSI Control Zero register is then read for an
	expected pattern of 0xc0.

    Processor 2 Data Path Test
	The Processor 2 Data Path  Test verifies the data lines to SCSI
	Processor 2. Patterns 0x00000000, 0x0000ffff, 0x00ff00ff,
	0x0f0f0f0f, 0x33333333, 0x55555555, and 0xffffffff are written
	to the processor Scratch Register A, read, and verified.

    Processor 2 Register-Register Test
	The Processor 2 Register-Register Test verifies that the
	processor can be initialized and run a simple script located in
	Local RAM that transfers 4 bytes from processor Scratch
	Register A to Scratch Register B.  A pattern of 0x01020304 is
	written into processor Scratch Register A. The processor DMA
	Scripts Pointer Register is written with  the address of the
	script in Local RAM forcing the processor to start executing
	the script. The processor Scratch Register B is read and the
	data verified.

    Processor 2 Interrupt Test
	The Processor 2 Interrupt Test verifies the SINT1 interrupt bit
	in the SCSI-16 Interrupt Status Register. The bit is checked
	for clear, the bit is checked for set after a small SCSI
	transfer, and the bit is checked for clear after writing the
	SCSI-16 Interrupt Status Register.

    Processor 2 Register-Local RAM Test
	The Processor 2 Register-Local RAM Test verifies that the
	processor can transfer 4 bytes from processor Scratch Register
	A to Local RAM.  A pattern of 0x01020304 is written into
	processor Scratch Register A. The processor transfers the 4
	bytes to a location in Local RAM. The data is read and
	verified.

    Processor 2 Local RAM-Register Test
	The Processor 2 Local RAM-Register Test verifies that the
	processor can transfer 4 bytes from a location in Local RAM to
	processor Scratch Register A.  A pattern of 0x01020304 is
	written into the location in Local RAM.  The processor
	transfers the 4 bytes to Scratch Register A. The data is read
	and verified.

    Processor 2 Local RAM-Local RAM Test
	The Processor 2 Local RAM-Local RAM Test verifies that the
	processor can transfer 64K bytes from a location in Local RAM
	to another location in Local RAM.  An incrementing byte pattern
	is written to one location in Local RAM. The processor
	transfers the 64K bytes to another location in Local RAM. The
	date is read and verified.

    Processor 2 Local RAM-Dual Port RAM Test
	The Processor 2 Local RAM-Dual Port RAM Test verifies that the
	processor can transfer 26K bytes from a location in Local RAM
	to a location in Dual Port RAM.  An incrementing byte pattern
	is written to the location in Local RAM. The processor
	transfers the 26K bytes to Dual Port RAM. The date is read and
	verified.

    Processor 2 Dual Port RAM-Local RAM Test
	The Processor 2 Dual Port RAM-Local RAM Test verifies that the
	processor can transfer 26K bytes from a location in Dual Port
	RAM to a location in Local RAM.  An incrementing byte pattern
	is written to the location in Dual Port RAM. The processor
	transfers the 26K bytes to Local RAM. The date is read and
	verified.

    Processor 2 Local RAM-Node RAM Test
	The Processor 2 Local RAM-Node RAM Test verifies that the
	processor can transfer 64K bytes from a location in Local RAM
	to a non-cached location in Node RAM.  An incrementing byte
	pattern is written to the location in Local RAM. The processor
	transfers the 64K bytes to Node RAM. The date is read and
	verified.

    Processor 2 Node RAM-Local RAM Test
	The Processor 2 Local RAM-Node RAM Test verifies that the
	processor can transfer 64K bytes from a non-cached location in
	Node RAM to a location in Local RAM.  An incrementing byte
	pattern is written to the location in Node RAM. The processor
	transfers the 64K bytes to Local RAM. The date is read and
	verified.

    Processor 2 Select Test
	The Processor 2 Select Test verifies that the processor can
	accomplish a SELECT sequence. The processor is put in loopback
	mode. The processor DMA Scripts Pointer Register is written
	with  the address of the script in Local RAM forcing the
	processor to start executing the SELECT script. When SEL goes
	high and BSY goes low, BSY is asserted by writing the processor
	Output Control Latch Register. The processor SCSI Bus Control
	Lines Register is read to verify that SEL went low.

    Processor 2 Select w/ATN Test
	The Processor 2 Select w/ATN Test verifies that the processor
	can accomplish a SELECT w/ATN sequence. The processor is put in
	loopback mode. After the processor has been Selected, the
	Output Control Latch Register is written with REQ, BSY, and MSG
	OUT. The processor Bus Data Lines Register is read to verify
	the proper MSG OUT.

    Processor 2 Command Descriptor Block Test
	The Processor 2 Command Descriptor Block Test verifies that the
	processor can accomplish a CDB sequence. The processor is put
	in loopback mode. A 6 byte pattern of 0x12, 0x34, 0x56, 0x78,
	0xab, and 0xcd is written to the processor. The processor Bus
	Data Lines Register is read to verify the pattern.

    Processor 2 Read Data Test
	The Processor 2 Read Data Test verifies that the processor can
	accomplish a DATA_IN sequence. The processor is put in loopback
	mode. A 5 byte pattern of 0x01, 0x02, 0x03, 0x04, and 0x05 is
	written to the processor Output Data Latch Register. The
	processor transfers the bytes to a buffer in Node RAM. The data
	is verified.

    Processor 2 Write Data Test
	The Processor 2 Write Data Test verifies that the processor can
	accomplish a DATA_OUT sequence. The processor is put in
	loopback mode. A 5 byte pattern of 0x01, 0x02, 0x03, 0x04, and
	0x05 is put in a buffer in Node RAM. The processor starts
	executing and the data is read from Node RAM into the
	processor. The processor Bus Data Lines Register is read and
	the data verified.


DMA Bypass Tests

The DMA Bypass Tests verify that data can be transferred between Local
RAM and Node RAM with 1 or both processors active. The transfer are
done with DMA Bypass on(ie. not using DMA logic).  Following is the DMA
Bypass Tests menu.

	Proc 1 Write(Local RAM->Node RAM) Test
	Proc 1 Read(Node RAM->Local RAM) Test
	Proc 2 Write(Local RAM->Node RAM) Test
	Proc 2 Read(Node RAM->Local RAM) Test
	Proc 1 & 2 Write(Local RAM->Node RAM) Test
	Proc 1 & 2 Read(Node RAM->Local RAM) Test
	Proc 1 & 2 Write/Read(Local RAM->Node RAM) Test
	Proc 1 & 2 Read/Write(Local RAM->Node RAM) Test
	Proc 1 & 2 Write(Local RAM->Node RAM) Backoff Test

    Proc 1 Write(Local RAM->Node RAM) Test
	The Proc 1 Write(Local RAM->Node RAM) Test verifies that the
	processor can transfer 64K bytes from Local RAM to Node RAM. A
	byte incrementing pattern is put into Local RAM and the
	processor is caused to execute a script. While the data is
	being transferred from Local RAM to Node RAM, a location in
	Local RAM is read every 1 millisecond to cause the processor to
	backoff. The data in Node RAM is verified.

    Proc 1 Read(Node RAM->Local RAM) Test
	The Proc 1 Read(Node RAM->Local RAM) Test verifies that the
	processor can transfer 64K bytes from Node RAM to Local RAM. A
	byte incrementing pattern is put into Node RAM and the
	processor is caused to execute a script. The data in Local RAM
	is verified.

    Proc 2 Write(Local RAM->Node RAM) Test
	The Proc 2 Write(Local RAM->NodeRAM) Test verifies that the
	processor can transfer 64K bytes from Local RAM to Node RAM. A
	byte incrementing pattern is put into Local RAM and the
	processor is caused to execute a script. The data in Node RAM
	is verified.

    Proc 2 Read(Node RAM->Local RAM) Test
	The Processor 2 Read(Node RAM->Local RAM) Test verifies that
	the processor can transfer 64K bytes from Node RAM to Local
	RAM. A byte incrementing pattern is put into Node RAM and the
	processor is caused to execute a script. The data in Local RAM
	is verified.

    Proc 1 & 2 Write(Local RAM->Node RAM) Test
	The Proc 1 & 2 Write(Local RAM->Node RAM) Test verifies that
	the both processors can transfer 64K bytes from Local RAM to
	Node RAM simultaneously. A byte incrementing pattern is put
	into Local RAM and the processors are caused to execute a
	script. The data in Node RAM is verified.

    Proc 1 & 2 Read(Node RAM->Local RAM) Test
	The Proc 1 & 2 Read(Node RAM->Local RAM) Test verifies that the
	both processors can transfer 64K bytes from Node RAM to Local
	RAM simultaneously. A byte incrementing pattern is put into
	Node RAM and the processors are caused to execute a script. The
	data in Local RAM is verified.

    Proc 1 & 2 Write/Read(Local RAM->Node RAM) Test
	The Proc 1 & 2 Write/Read(Local RAM->Node RAM) Test verifies
	that the both processors can transfer 64K bytes
	simultaneously. Processor 1 transfers bytes from Local RAM to
	Node RAM and processor 2 transfers bytes from Node RAM to Local
	RAM. A byte incrementing pattern is put into a Local RAM buffer
	and a Node RAM buffer. The processors are caused to execute a
	script. The data in Local RAM and Node RAM is verified.

    Proc 1 & 2 Read/Write(Local RAM->Node RAM) Test
	The Proc 1 & 2 Read/Write(Local RAM->Node RAM) Test verifies
	that the both processors can transfer 64K bytes
	simultaneously. Processor 1 transfers bytes from Node RAM to
	Local RAM and processor 2 transfers bytes from Local RAM to
	Node RAM. A byte incrementing pattern is put into a Local RAM
	buffer and a Node RAM buffer. The processors are caused to
	execute a script. The data in Local RAM and Node RAM is
	verified.

    Proc 1 & 2 Write(Local RAM->Node RAM) Backoff Test
	The Proc 1 & 2 Write(Local RAM->Node RAM) Test verifies that
	both processors can transfer 64K bytes from Local RAM to Node
	RAM simultaneously. A byte incrementing pattern is put into 2
	buffers in Local RAM and the processors are caused to execute a
	script. While the data is being transferred from Local RAM to
	Node RAM, a location in Local RAM is read every 1 millisecond
	to cause the processors to backoff. The data in both buffers in
	Node RAM is verified.


DMA Controller Tests

The DMA Controller Tests verify that data can be transferred between
Local RAM and Node RAM with 1 or both processors active. DMA Channel
interrupts, misalinged transfers, and an Ethernet transfer are checked.
The transfer are done with DMA Bypass off(ie. using DMA logic).
Following is the DMA Controller Tests menu.

	Proc 1 DMA Write Block Test
	Proc 1 DMA Channel 0 Interrupt Test
	Proc 1 DMA Read Block Test
	Proc 2 DMA Write Block Test
	Proc 2 DMA Channel 1 Interrupt Test
	Proc 2 DMA Read Block Test
	Proc 1 & 2 DMA Write(Local RAM->Node RAM) Test
	Proc 1 & 2 DMA Read(Node RAM->Local RAM) Test
	Proc 1 & 2 DMA Write/Read(Local RAM->Node RAM) Test
	Proc 1 & 2 DMA Read/Write(Local RAM->Node RAM) Test
	Proc 1 & 2 DMA Write(Local RAM->Node RAM) Backoff Test
	Proc 1 DMA Write Large Block Test
	Proc 1 DMA Read Large Block Test
	Proc 1 DMA Write Misaligned Block Test
	Proc 1 DMA Read Misaligned Block Test
	Ethernet DMA(Local RAM->Node RAM) Test

    Proc 1 DMA Write Block Test
	The Proc 1 DMA Write Block Test verifies that the processor can
	transfer 1K bytes from Local RAM to Node RAM. A byte
	incrementing pattern is put into Local RAM and the processor is
	caused to execute a script. The 1K bytes of data in Node RAM
	are verified and the 63K bytes of unused data are verified to
	be zero.

    Proc 1 DMA Channel 0 Interrupt Test
	The Proc 1 DMA Channel 0 Interrupt Test verifies the DINT0
	interrupt bit in the SCSI-16 Interrupt Status Register. The bit
	is checked for clear, the bit is checked for set after a small
	DMA transfer, and the bit is checked for clear after writing
	the SCSI-16 Interrupt Status Register.

    Proc 1 DMA Read Block Test
	The Proc 1 DMA Read Block Test verifies that the processor can
	transfer 2K bytes from Node RAM to Local RAM. A byte
	incrementing pattern is put into Node RAM and the processor is
	caused to execute a script. The 2K bytes of data in Local RAM
	are verified and the 62K bytes of unused data are verified to
	be zero.

    Proc 2 DMA Write Block Test
	The Proc 2 DMA Write Block Test verifies that the processor can
	transfer 1K bytes from Local RAM to Node RAM. A byte
	incrementing pattern is put into Local RAM and the processor is
	caused to execute a script. The 1K bytes of data in Node RAM
	are verified and the 63K bytes of unused data are verified to
	be zero.

    Proc 2 DMA Channel 1 Interrupt Test
	The Proc 2 DMA Channel 1 Interrupt Test verifies the DINT1
	interrupt bit in the SCSI-16 Interrupt Status Register. The bit
	is checked for clear, the bit is checked for set after a small
	DMA transfer, and the bit is checked for clear after writing
	the SCSI-16 Interrupt Status Register.

    Proc 2 DMA Read Block Test
	The Proc 2 DMA Read Block Test verifies that the processor can
	transfer 2K bytes from Node RAM to Local RAM. A byte
	incrementing pattern is put into Node RAM and the processor is
	caused to execute a script. The 2K bytes of data in Local RAM
	are verified and the 62K bytes of unused data are verified to
	be zero.

    Proc 1 & 2 DMA Write(LRAM->Node RAM) Test
	The Proc 1 & 2 DMA Write(LRAM->Node RAM) Test verifies that the
	both processors can transfer 16K bytes from Local RAM to Node
	RAM simultaneously. A byte incrementing pattern is put into
	Local RAM and the processors are caused to execute a script.
	The data in Node RAM is verified.

    Proc 1 & 2 DMA Read(Node RAM->LRAM) Test
	The Proc 1 & 2 DMA Read(Node RAM->LRAM) Test verifies that the
	both processors can transfer 16K bytes from Node RAM to Local
	RAM simultaneously. A byte incrementing pattern is put into
	Node RAM and the processors are caused to execute a script. The
	data in Local RAM is verified.

    Proc 1 & 2 DMA Write/Read(LRAM->Node) Test
	The Proc 1 & 2 DMA Write/Read(LRAM->Node RAM) Test verifies
	that the both processors can transfer 16K bytes
	simultaneously. Processor 1 transfers bytes from Local RAM to
	Node RAM and processor 2 transfers bytes from Node RAM to Local
	RAM. A byte incrementing pattern is put into a Local RAM buffer
	and a Node RAM buffer. The processors are caused to execute a
	script. The data in Local RAM and Node RAM is verified.

    Proc 1 & 2 DMA Read/Write(LRAM->Node) Test
	The Proc 1 & 2 DMA Read/Write(LRAM->Node RAM) Test verifies
	that the both processors can transfer 16K bytes
	simultaneously. Processor 1 transfers bytes from Node RAM to
	Local RAM and processor 2 transfers bytes from Local RAM to
	Node RAM. A byte incrementing pattern is put into a Local RAM
	buffer and a Node RAM buffer. The processors are caused to
	execute a script. The data in Local RAM and Node RAM is
	verified.

    Proc 1 & 2 DMA Write(LRAM->Node) Backoff Test
	The Proc 1 & 2 DMA Write(LRAM->Node RAM) Test verifies that
	both processors can transfer 16K bytes from Local RAM to Node
	RAM simultaneously. A byte incrementing pattern is put into 2
	buffers in Local RAM and the processors are caused to execute a
	script. While the data is being transferred from Local RAM to
	Node RAM, a location in Local RAM is read every 1 millisecond
	to cause the processors to backoff. The data in both buffers in
	Node RAM is verified.

    Proc1 DMA Write Large Block Test
	The Proc 1 DMA Write Large Block Test verifies that the
	processor can transfer 64K bytes from Local RAM to Node RAM. A
	byte incrementing pattern is put into Local RAM and the
	processor is caused to execute a script. The data in Node RAM
	is verified.

    Proc1 DMA Read Large Block Test
	The Proc 1 DMA Read Large Block Test verifies that the
	processor can transfer 64K bytes from Node RAM to Local RAM. A
	byte incrementing pattern is put into Node RAM and the
	processor is caused to execute a script. The data in Local RAM
	is verified.

    Proc 1 DMA Write Misaligned Block Test
	The Proc 1 DMA Write Misaligned Block Test verifies that the
	processor can transfer 4K bytes from Local RAM to Node RAM on a
	misaligned boundary. A byte incrementing pattern with a block
	number inserted every 512 bytes is put into Local RAM and the
	processor is caused to execute a script. The data in Node RAM
	is verified.

    Proc 1 DMA Read Misaligned Block Test
	The Proc 1 DMA Read Misaligned Block Test verifies that the
	processor can transfer 4K bytes from Node RAM to Local RAM on a
	misaligned boundary. A byte incrementing pattern with a block
	number inserted every 512 bytes is put into Node RAM and the
	processor is caused to execute a script. The data in Local RAM
	is verified.

    Ethernet DMA(Local RAM->Node RAM) Test
	The Ethernet DMA(Local RAM->Node RAM) Test verifies the DMA
	Controller logic for ethernet DMA transfers. The 82596 is
	placed in internal loopback mode and a 1664 byte packet is
	transferred from Local RAM to Node RAM. The receive buffer
	descriptors point to 128 byte memory segments which are aligned
	on an increasing power of 2 address boundary(ie. 0, 128, 256,
	512, 1024, 2048...). The data is verified.


SCSI Proc 1 DMA Bypass Cache Coherency Tests

The SCSI Proc 1 DMA Bypass Cache Coherency Tests ensure that the data
loaded in i860-XP processor cache is flushed out properly when an
access by the SCSI-16 expansion card occurs on the processor bus. All
of the tests described below use the same high level algorithm. Each
test is differentiated by the memory access patterns generated which
affect the processor cache.

The high level testing algorithm follows:

    foreach MP or GP node processor:
      loop test specific times with memory address increment:
          - initialize a non-cached memory(BG) pattern
          - setup the SCSI processor for a transfer
          - Flush and enable the i860 processor cache
            place data into the processor cache (test dependent)
          - initiate a SCSI processor transfer to clean out the cache
          - check and report transfer errors
          - flush and disable the i860 processor cache

Each test may be run in DMA Bypass Off or DMA Bypass On mode by either
SCSI processor. The following sections describe the differences in
cache access patterns. Local RAM addresses not mentioned below for
transfer addresses are 0x80710000 unless otherwise stated. All scripts
are located at 0x80700000. The data placed into the processor cache
will always be at the stated transfer address.

Following is the SCSI Proc 1 DMA Bypass Cache Coherency Tests menu.
These tests use SCSI Processor 1 with no DMA logic involved:

	Coherent Read & Flush Test
	Single Write Invalidate Test
	Increment with loop Write Invalidate Test
	Single Byte Gather Node->LRAM Test
	16 Byte Gather Node RAM->LRAM Test
	Walking 16 Byte Gather Node->LRAM Test
	Aligned Small Block Node->LRAM Test
	Aligned Small Block LRAM->Node Test
	Unaligned Sliding 8K LRAM->Node Test
	Unaligned Sliding 8K Node->LRAM Test
	All Node Processors Interleave Test

    Coherent Read & Flush Test
	The Coherent Read & Flush Test ensures that data from the i860
	cache lines can be read properly. The test loops 24 times.
	Transfer memory addresses start at 0xe0c00000 with an address
	increment of 16 for each loop. The SCSI processor reads 12
	bytes from the cache block and transfers it into Local RAM. The
	data is verified.

    Single Write Invalidate Test
	The Single Write Invalidate Test ensures that data from the
	i860 cache is flushed and invalidated properly. Transfer memory
	address is 0xe0c00000 and there is only one loop. The SCSI
	processor reads 3 bytes from Local RAM at 0x80720000 with byte
	offsets of 0, 4, and 8. Each byte is transferred to the
	corresponding byte offset of the transfer memory address. The
	SCSI processor then reads 12 bytes from the transfer memory
	address and places the data in Local RAM at 0x80710000. The
	data is verified.

    Increment with loop Write Invalidate Test
	The Increment with loop Write Invalidate Test is the same as
	the Single Write Invalidate test except the loop count is 24
	and the address increment is 32.

    Single Byte Gather Node->LRAM Test
	The Single Byte Gather Node->LRAM Test ensures that data from
	multiple i860 cache lines can be read properly. The test loops
	24 times. Transfer memory addresses start at 0xE0C00000 with an
	address increment of 32 for each loop. Block size 32. The SCSI
	processor reads 1 byte from each block in an incrementing
	address pattern (eg. cache block byte 0 in block 0, byte 1 in
	block one, byte 22 in block 22).  22 blocks are affected of
	which 9 have modified data (blocks 1, 4, 5, 13, 15, 16, 18, 19,
	20).  Local RAM contains 22 bytes of data at the end of the
	test.

    16 Byte Gather Node->LRAM Test
	The 16 Byte Gather Node->LRAM Test ensures that data from
	multiple i860 cache lines can be read properly. The test loops
	24 times. Transfer memory addresses start at 0xE0C00000 with an
	address increment of 0x220 for each loop. Block size 32. The
	SCSI processor reads 16 bytes from each block in an
	incrementing address pattern (eg. cache block word 0 in block
	0, word 1 in block one, word 22 in block 22, word size is 4
	bytes). 22 blocks are affected of which 9 have modified data
	(blocks 1, 4, 5, 13, 15, 16, 18, 19, 20).  Local RAM contains
	352 bytes of data at the end of the test.

    Walking 16 Byte Gather Node->LRAM Test
	The Walking 16 Byte Gather Node->LRAM Test ensures that data
	from multiple i860 cache lines can be read properly. The test
	loops 24 times. Transfer memory addresses start at 0xE0C00000
	with an address increment of 0x1f00 for each loop. Block size
	36. The SCSI processor reads 16 bytes from each block in an
	incrementing address pattern (eg. block word 0 in block 0, word
	1 in block one, word 22 in block 22, word size is 4 bytes). 22
	blocks  are affected of which 9 have modified data (blocks 1,
	4, 5, 13, 15, 16, 18, 19, 20).  Local RAM contains 352 bytes of
	data at the end of the test.

    Aligned Small Block Node->LRAM Test
	The Aligned Small Block Node->LRAM Test ensures that data from
	multiple i860 cache lines can be read properly. The test loops
	24 times. Transfer memory addresses start at 0xE0C00000 with an
	address increment of 0x3C0 for each loop. Block size 32. The
	SCSI processor reads 704 bytes from main memory.  The i860
	processor will have some of these 704 bytes cached in an
	incrementing pattern. 22 blocks are affected of which 9 have
	modified data (blocks 1, 4, 5, 13, 15, 16, 18, 19, 20).  Local
	RAM contains 704 bytes of data at the end of the test.

    Aligned Small Block LRAM->Node Test
	The Aligned Small Block LRAM->Node Test ensures that data from
	multiple i860 cache lines can be invalidated properly. The test
	loops 24 times. Transfer memory addresses start at 0xE0C00000
	with an address increment of 0x300 for each loop. Block size
	32. The SCSI processor writes 704 bytes to main memory. 22
	blocks are affected of which 9 have modified data (blocks 1, 4,
	5, 13, 15, 16, 18, 19, 20). This modified data will be over
	written by the data patterns from Local Ram during the
	transfer.

    Unaligned Sliding 8K LRAM->Node Test
	The Unaligned Sliding 8K LRAM->Node Test ensures that data from
	multiple i860 cache lines can be invalidated properly. The test
	loops 33 times. Transfer memory addresses start at 0xE0C00000
	with an address increment of 1 for each loop. Block size 32.
	The SCSI processor writes 8224 bytes to main memory.  The i860
	processor will have some of these 8224 bytes cached. 257 blocks
	are affected of which 36 have modified data (blocks 0, 2, 5, 8,
	15, 16, 18, 19, 20, 51, 54, 58, 63, 65, 66, 68, 69, 70, 150,
	151, 152, 153, 154, 181, 182, 183, 190, 218, 219, 221, 222,
	226, 229, 231, 232, 234). This modified data will be over
	written by the data patterns from Local RAM during the
	transfer.

    Unaligned Sliding 8K Node->LRAM Test
	The Unaligned Sliding 8K Node->LRAM Test ensures that data from
	multiple i860 cache lines can be read properly. The test loops
	33 times.  Transfer memory addresses start at 0xE0C00000 with
	an address increment of 1 for each loop. Block size 32.  The
	NCR processor reads 8224 bytes from main memory.  The i860
	processor will have some of these 8224 bytes cached.  There are
	257 blocks that are affected of which 36 have modified data
	(blocks 0, 2, 5, 8, 15, 16, 18, 19, 20, 51, 54, 58, 63, 65, 66,
	68, 69, 70, 150, 151, 152, 153, 154, 181, 182, 183, 190, 218,
	219, 221, 222, 226, 229, 231, 232, 234). This modified data
	will be written to Local RAM.

    All Node Processors Interleave Test
	The All Node Processors Interleave Test ensures that multiple
	processors that have modified data cached will be flushed when
	a transfer occurs from the SCSI processors. The test algorithm
	is:
	    loop 50 times with address increment of 32
              - start all processors
              - have each processor initialize a back ground pattern
              - each processor enables cache
              - barrier sync
              - the system processor initializes a 65K transfer in the SCSI proc
              - barrier sync
              - each processor loads up its cache
              - barrier sync
              - the system processor starts the transfer
              - barrier sync
              - each processor checks its data for errors and reports them
              - each processor disables and flushes cache
              - barrier sync

	Each processor will load data into its cache in a manner which
	will ensure that the data was modified in the cache. The SCSI
	processor transfer will be flushing these caches and there will
	be adjacent memory addressed cache blocks which are modified in
	different processors.  If all testing loops complete with no
	errors then the test passes.


SCSI Proc 2 DMA Bypass Cache Coherency Tests

The SCSI Proc 2 DMA Bypass Cache Coherency Tests are identical to those
previous except for using SCSI Processor 2 as the transfer agent. DMA
bypass is used which means no DMA logic is involved. Only the menu will
shown here since the descriptions of the tests are the same.
Following is the SCSI Proc 2 DMA Bypass Cache Coherency Tests menu:

	Coherent Read & Flush Test
	Single Write Invalidate Test
	Increment with loop Write Invalidate Test
	Single Byte Gather Node->LRAM Test
	16 Byte Gather Node RAM->LRAM Test
	Walking 16 Byte Gather Node->LRAM Test
	Aligned Small Block Node->LRAM Test
	Aligned Small Block LRAM->Node Test
	Unaligned Sliding 8K LRAM->Node Test
	Unaligned Sliding 8K Node->LRAM Test
	All Node Processors Interleave Test


SCSI Proc 1 DMA Cache Coherency Tests

The SCSI Proc 1 DMA Cache Coherency Tests are identical to those
previous except for using SCSI Processor 1 as the transfer agent. DMA
is used which means DMA logic IS involved.  Only the menu will shown
here since the descriptions of the tests are the same.  Following is the 
SCSI Proc 1 DMA Cache Coherency Tests menu:

	Coherent Read & Flush Test
	Single Write Invalidate Test
	Increment with loop Write Invalidate Test
	Single Byte Gather Node->LRAM Test
	16 Byte Gather Node RAM->LRAM Test
	Walking 16 Byte Gather Node->LRAM Test
	Aligned Small Block Node->LRAM Test
	Aligned Small Block LRAM->Node Test
	Unaligned Sliding 8K LRAM->Node Test
	Unaligned Sliding 8K Node->LRAM Test
	All Node Processors Interleave Test


SCSI Proc 2 DMA Cache Coherency Tests

The SCSI Proc 2 DMA Cache Coherency Tests are identical to those
previous except for using SCSI Processor 2 as the transfer agent. DMA
is used which means DMA logic IS involved. Only the menu will shown
here since the descriptions of the tests are the same.  Following is
the SCSI Proc 2 DMA Cache Coherency Tests menu:

	Coherent Read & Flush Test
	Single Write Invalidate Test
	Increment with loop Write Invalidate Test
	Single Byte Gather Node->LRAM Test
	16 Byte Gather Node RAM->LRAM Test
	Walking 16 Byte Gather Node->LRAM Test
	Aligned Small Block Node->LRAM Test
	Aligned Small Block LRAM->Node Test
	Unaligned Sliding 8K LRAM->Node Test
	Unaligned Sliding 8K Node->LRAM Test
	All Node Processors Interleave Test

