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- Features
- Configuration Bits
- RAM map
- SFR map

PIC18C252
CONFIG1L (address:0x300000, mask:0xFF)
CP -- Code Protection bits
| CP = ON | 0x00 | All of program memory code protected. |
| CP = OFF | 0xFF | Program memory code protection off. |
CONFIG1H (address:0x300001, mask:0xE7)
OSC -- Oscillator Selection bits
| OSC = LP | 0xF8 | LP oscillator. |
| OSC = XT | 0xF9 | XT oscillator. |
| OSC = HS | 0xFA | HS oscillator. |
| OSC = RC | 0xFB | RC oscillator. |
| OSC = EC | 0xFC | EC oscillator w/OSC2 configured as divide-by-4 clock output. |
| OSC = ECIO | 0xFD | EC oscillator w/OSC2 configured as RA6. |
| OSC = HSPLL | 0xFE | HS oscillator with PLL enabled/Clock frequency = (4 x FOSC). |
| OSC = RCIO | 0xFF | RC oscillator w/OSC2 configured as RA6. |
OSCS -- Oscillator System Clock Switch Enable bit
| OSCS = ON | 0xDF | Oscillator system clock switch option is enabled (oscillator switching is enabled). |
| OSCS = OFF | 0xFF | Oscillator system clock switch option is disabled (main oscillator is source). |
CONFIG2L (address:0x300002, mask:0x0F)
PWRT -- Power-up Timer Enable bit
| PWRT = ON | 0xFE | PWRT enabled. |
| PWRT = OFF | 0xFF | PWRT disabled. |
BOR -- Brown-out Reset Enable bit
| BOR = OFF | 0xFD | Brown-out Reset disabled. |
| BOR = ON | 0xFF | Brown-out Reset enabled. |
BORV -- Brown-out Reset Voltage bits
| BORV = 45 | 0xF3 | VBOR set to 4.5V. |
| BORV = 42 | 0xF7 | VBOR set to 4.2V. |
| BORV = 27 | 0xFB | VBOR set to 2.7V. |
| BORV = 25 | 0xFF | VBOR set to 2.5V. |
CONFIG2H (address:0x300003, mask:0x0F)
WDT -- Watchdog Timer Enable bit
| WDT = OFF | 0xFE | WDT disabled (control is placed on the SWDTEN bit). |
| WDT = ON | 0xFF | WDT enabled. |
WDTPS -- Watchdog Timer Postscale Select bits
| WDTPS = 1 | 0xF1 | 1:1. |
| WDTPS = 2 | 0xF3 | 1:2. |
| WDTPS = 4 | 0xF5 | 1:4. |
| WDTPS = 8 | 0xF7 | 1:8. |
| WDTPS = 16 | 0xF9 | 1:16. |
| WDTPS = 32 | 0xFB | 1:32. |
| WDTPS = 64 | 0xFD | 1:64. |
| WDTPS = 128 | 0xFF | 1:128. |
CONFIG3H (address:0x300005, mask:0x01)
CCP2MUX -- CCP2 Mux bit
| CCP2MUX = OFF | 0xFE | CCP2 input/output is multiplexed with RB3. |
| CCP2MUX = ON | 0xFF | CCP2 input/output is multiplexed with RC1. |
CONFIG4L (address:0x300006, mask:0x03)
STVR -- Stack Full/Underflow Reset Enable bit
| STVR = OFF | 0xFE | Stack Full/Underflow will not cause RESET. |
| STVR = ON | 0xFF | Stack Full/Underflow will cause RESET. |

This page generated automatically by the device-help.pl program (2012-12-22 23:50:59 UTC) from the 8bit_device.info file (rev: 1.10) of mpasmx and from the gputils source package (rev: svn 918). The mpasmx is included in the MPLAB X.