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- Features
- Configuration Bits
- RAM map
- SFR map

PIC18F2455
CONFIG1L (address:0x300000, mask:0x00)
PLLDIV -- PLL Prescaler Selection bits
| PLLDIV = 1 | 0xF8 | No prescale (4 MHz oscillator input drives PLL directly). |
| PLLDIV = 2 | 0xF9 | Divide by 2 (8 MHz oscillator input). |
| PLLDIV = 3 | 0xFA | Divide by 3 (12 MHz oscillator input). |
| PLLDIV = 4 | 0xFB | Divide by 4 (16 MHz oscillator input). |
| PLLDIV = 5 | 0xFC | Divide by 5 (20 MHz oscillator input). |
| PLLDIV = 6 | 0xFD | Divide by 6 (24 MHz oscillator input). |
| PLLDIV = 10 | 0xFE | Divide by 10 (40 MHz oscillator input). |
| PLLDIV = 12 | 0xFF | Divide by 12 (48 MHz oscillator input). |
CPUDIV -- System Clock Postscaler Selection bits
| CPUDIV = OSC1_PLL2 | 0xE7 | [Primary Oscillator Src: /1][96 MHz PLL Src: /2]. |
| CPUDIV = OSC2_PLL3 | 0xEF | [Primary Oscillator Src: /2][96 MHz PLL Src: /3]. |
| CPUDIV = OSC3_PLL4 | 0xF7 | [Primary Oscillator Src: /3][96 MHz PLL Src: /4]. |
| CPUDIV = OSC4_PLL6 | 0xFF | [Primary Oscillator Src: /4][96 MHz PLL Src: /6]. |
USBDIV -- USB Clock Selection bit (used in Full-Speed USB mode only; UCFG:FSEN = 1)
| USBDIV = 1 | 0xDF | USB clock source comes directly from the primary oscillator block with no postscale. |
| USBDIV = 2 | 0xFF | USB clock source comes from the 96 MHz PLL divided by 2. |
CONFIG1H (address:0x300001, mask:0x05)
FOSC -- Oscillator Selection bits
| FOSC = XT_XT | 0xF0 | XT oscillator (XT). |
| FOSC = XTPLL_XT | 0xF2 | XT oscillator, PLL enabled (XTPLL). |
| FOSC = ECIO_EC | 0xF4 | EC oscillator, port function on RA6 (ECIO). |
| FOSC = EC_EC | 0xF5 | EC oscillator, CLKO function on RA6 (EC). |
| FOSC = ECPLLIO_EC | 0xF6 | EC oscillator, PLL enabled, port function on RA6 (ECPIO). |
| FOSC = ECPLL_EC | 0xF7 | EC oscillator, PLL enabled, CLKO function on RA6 (ECPLL). |
| FOSC = INTOSCIO_EC | 0xF8 | Internal oscillator, port function on RA6, EC used by USB (INTIO). |
| FOSC = INTOSC_EC | 0xF9 | Internal oscillator, CLKO function on RA6, EC used by USB (INTCKO). |
| FOSC = INTOSC_XT | 0xFA | Internal oscillator, XT used by USB (INTXT). |
| FOSC = INTOSC_HS | 0xFB | Internal oscillator, HS oscillator used by USB (INTHS). |
| FOSC = HS | 0xFC | HS oscillator (HS). |
| FOSC = HSPLL_HS | 0xFE | HS oscillator, PLL enabled (HSPLL). |
FCMEN -- Fail-Safe Clock Monitor Enable bit
| FCMEN = OFF | 0xBF | Fail-Safe Clock Monitor disabled. |
| FCMEN = ON | 0xFF | Fail-Safe Clock Monitor enabled. |
IESO -- Internal/External Oscillator Switchover bit
| IESO = OFF | 0x7F | Oscillator Switchover mode disabled. |
| IESO = ON | 0xFF | Oscillator Switchover mode enabled. |
CONFIG2L (address:0x300002, mask:0x1F)
PWRT -- Power-up Timer Enable bit
| PWRT = ON | 0xFE | PWRT enabled. |
| PWRT = OFF | 0xFF | PWRT disabled. |
BOR -- Brown-out Reset Enable bits
| BOR = OFF | 0xF9 | Brown-out Reset disabled in hardware and software. |
| BOR = SOFT | 0xFB | Brown-out Reset enabled and controlled by software (SBOREN is enabled). |
| BOR = ON_ACTIVE | 0xFD | Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled). |
| BOR = ON | 0xFF | Brown-out Reset enabled in hardware only (SBOREN is disabled). |
BORV -- Brown-out Reset Voltage bits
| BORV = 0 | 0xE7 | Maximum setting. |
| BORV = 1 | 0xEF |  |
| BORV = 2 | 0xF7 |  |
| BORV = 3 | 0xFF | Minimum setting. |
VREGEN -- USB Voltage Regulator Enable bit
| VREGEN = OFF | 0xDF | USB voltage regulator disabled. |
| VREGEN = ON | 0xFF | USB voltage regulator enabled. |
CONFIG2H (address:0x300003, mask:0x1F)
WDT -- Watchdog Timer Enable bit
| WDT = OFF | 0xFE | WDT disabled (control is placed on the SWDTEN bit). |
| WDT = ON | 0xFF | WDT enabled. |
WDTPS -- Watchdog Timer Postscale Select bits
| WDTPS = 1 | 0xE1 | 1:1. |
| WDTPS = 2 | 0xE3 | 1:2. |
| WDTPS = 4 | 0xE5 | 1:4. |
| WDTPS = 8 | 0xE7 | 1:8. |
| WDTPS = 16 | 0xE9 | 1:16. |
| WDTPS = 32 | 0xEB | 1:32. |
| WDTPS = 64 | 0xED | 1:64. |
| WDTPS = 128 | 0xEF | 1:128. |
| WDTPS = 256 | 0xF1 | 1:256. |
| WDTPS = 512 | 0xF3 | 1:512. |
| WDTPS = 1024 | 0xF5 | 1:1024. |
| WDTPS = 2048 | 0xF7 | 1:2048. |
| WDTPS = 4096 | 0xF9 | 1:4096. |
| WDTPS = 8192 | 0xFB | 1:8192. |
| WDTPS = 16384 | 0xFD | 1:16384. |
| WDTPS = 32768 | 0xFF | 1:32768. |
CONFIG3H (address:0x300005, mask:0x83)
CCP2MX -- CCP2 MUX bit
| CCP2MX = OFF | 0xFE | CCP2 input/output is multiplexed with RB3. |
| CCP2MX = ON | 0xFF | CCP2 input/output is multiplexed with RC1. |
PBADEN -- PORTB A/D Enable bit
| PBADEN = OFF | 0xFD | PORTB<4:0> pins are configured as digital I/O on Reset. |
| PBADEN = ON | 0xFF | PORTB<4:0> pins are configured as analog input channels on Reset. |
LPT1OSC -- Low-Power Timer 1 Oscillator Enable bit
| LPT1OSC = OFF | 0xFB | Timer1 configured for higher power operation. |
| LPT1OSC = ON | 0xFF | Timer1 configured for low-power operation. |
MCLRE -- MCLR Pin Enable bit
| MCLRE = OFF | 0x7F | RE3 input pin enabled; MCLR pin disabled. |
| MCLRE = ON | 0xFF | MCLR pin enabled; RE3 input pin disabled. |
CONFIG4L (address:0x300006, mask:0x85)
STVREN -- Stack Full/Underflow Reset Enable bit
| STVREN = OFF | 0xFE | Stack full/underflow will not cause Reset. |
| STVREN = ON | 0xFF | Stack full/underflow will cause Reset. |
LVP -- Single-Supply ICSP Enable bit
| LVP = OFF | 0xFB | Single-Supply ICSP disabled. |
| LVP = ON | 0xFF | Single-Supply ICSP enabled. |
XINST -- Extended Instruction Set Enable bit
| XINST = OFF | 0xBF | Instruction set extension and Indexed Addressing mode disabled (Legacy mode). |
| XINST = ON | 0xFF | Instruction set extension and Indexed Addressing mode enabled. |
DEBUG -- Background Debugger Enable bit
| DEBUG = ON | 0x7F | Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug. |
| DEBUG = OFF | 0xFF | Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins. |
CONFIG5L (address:0x300008, mask:0x0F)
CP0 -- Code Protection bit
| CP0 = ON | 0xFE | Block 0 (000800-001FFFh) is code-protected. |
| CP0 = OFF | 0xFF | Block 0 (000800-001FFFh) is not code-protected. |
CP1 -- Code Protection bit
| CP1 = ON | 0xFD | Block 1 (002000-003FFFh) is code-protected. |
| CP1 = OFF | 0xFF | Block 1 (002000-003FFFh) is not code-protected. |
CP2 -- Code Protection bit
| CP2 = ON | 0xFB | Block 2 (004000-005FFFh) is code-protected. |
| CP2 = OFF | 0xFF | Block 2 (004000-005FFFh) is not code-protected. |
CONFIG5H (address:0x300009, mask:0xC0)
CPB -- Boot Block Code Protection bit
| CPB = ON | 0xBF | Boot block (000000-0007FFh) is code-protected. |
| CPB = OFF | 0xFF | Boot block (000000-0007FFh) is not code-protected. |
CPD -- Data EEPROM Code Protection bit
| CPD = ON | 0x7F | Data EEPROM is code-protected. |
| CPD = OFF | 0xFF | Data EEPROM is not code-protected. |
CONFIG6L (address:0x30000A, mask:0x0F)
WRT0 -- Write Protection bit
| WRT0 = ON | 0xFE | Block 0 (000800-001FFFh) is write-protected. |
| WRT0 = OFF | 0xFF | Block 0 (000800-001FFFh) is not write-protected. |
WRT1 -- Write Protection bit
| WRT1 = ON | 0xFD | Block 1 (002000-003FFFh) is write-protected. |
| WRT1 = OFF | 0xFF | Block 1 (002000-003FFFh) is not write-protected. |
WRT2 -- Write Protection bit
| WRT2 = ON | 0xFB | Block 2 (004000-005FFFh) is write-protected. |
| WRT2 = OFF | 0xFF | Block 2 (004000-005FFFh) is not write-protected. |
CONFIG6H (address:0x30000B, mask:0xE0)
WRTC -- Configuration Register Write Protection bit
| WRTC = ON | 0xDF | Configuration registers (300000-3000FFh) are write-protected. |
| WRTC = OFF | 0xFF | Configuration registers (300000-3000FFh) are not write-protected. |
WRTB -- Boot Block Write Protection bit
| WRTB = ON | 0xBF | Boot block (000000-0007FFh) is write-protected. |
| WRTB = OFF | 0xFF | Boot block (000000-0007FFh) is not write-protected. |
WRTD -- Data EEPROM Write Protection bit
| WRTD = ON | 0x7F | Data EEPROM is write-protected. |
| WRTD = OFF | 0xFF | Data EEPROM is not write-protected. |
CONFIG7L (address:0x30000C, mask:0x0F)
EBTR0 -- Table Read Protection bit
| EBTR0 = ON | 0xFE | Block 0 (000800-001FFFh) is protected from table reads executed in other blocks. |
| EBTR0 = OFF | 0xFF | Block 0 (000800-001FFFh) is not protected from table reads executed in other blocks. |
EBTR1 -- Table Read Protection bit
| EBTR1 = ON | 0xFD | Block 1 (002000-003FFFh) is protected from table reads executed in other blocks. |
| EBTR1 = OFF | 0xFF | Block 1 (002000-003FFFh) is not protected from table reads executed in other blocks. |
EBTR2 -- Table Read Protection bit
| EBTR2 = ON | 0xFB | Block 2 (004000-005FFFh) is protected from table reads executed in other blocks. |
| EBTR2 = OFF | 0xFF | Block 2 (004000-005FFFh) is not protected from table reads executed in other blocks. |
CONFIG7H (address:0x30000D, mask:0x40)
EBTRB -- Boot Block Table Read Protection bit
| EBTRB = ON | 0xBF | Boot block (000000-0007FFh) is protected from table reads executed in other blocks. |
| EBTRB = OFF | 0xFF | Boot block (000000-0007FFh) is not protected from table reads executed in other blocks. |

This page generated automatically by the device-help.pl program (2012-12-22 23:51:00 UTC) from the 8bit_device.info file (rev: 1.10) of mpasmx and from the gputils source package (rev: svn 918). The mpasmx is included in the MPLAB X.