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- Features
- Configuration Bits
- RAM map
- SFR map

PIC18F1320
CONFIG1H (address:0x300001, mask:0xCF)
OSC -- Oscillator Selection bits
| OSC = LP | 0xF0 | LP Oscillator. |
| OSC = XT | 0xF1 | XT Oscillator. |
| OSC = HS | 0xF2 | HS Oscillator. |
| OSC = EC | 0xF4 | EC oscillator, CLKO function on RA6. |
| OSC = ECIO | 0xF5 | EC oscillator, port function on RA6. |
| OSC = HSPLL | 0xF6 | HS oscillator, PLL enabled (clock frequency = 4 x FOSC1). |
| OSC = RCIO | 0xF7 | External RC oscillator, port function on RA6. |
| OSC = INTIO2 | 0xF8 | Internal RC oscillator, port function on RA6 and port function on RA7. |
| OSC = INTIO1 | 0xF9 | Internal RC oscillator, CLKO function on RA6 and port function on RA7. |
| OSC = RC | 0xFC | External RC oscillator, CLKO function on RA6. |
FSCM -- Fail-Safe Clock Monitor Enable bit
| FSCM = OFF | 0xBF | Fail-Safe Clock Monitor disabled. |
| FSCM = ON | 0xFF | Fail-Safe Clock Monitor enabled. |
IESO -- Internal External Switchover bit
| IESO = OFF | 0x7F | Internal External Switchover mode disabled. |
| IESO = ON | 0xFF | Internal External Switchover mode enabled. |
CONFIG2L (address:0x300002, mask:0x0F)
PWRT -- Power-up Timer Enable bit
| PWRT = ON | 0xFE | PWRT enabled. |
| PWRT = OFF | 0xFF | PWRT disabled. |
BOR -- Brown-out Reset Enable bit
| BOR = OFF | 0xFD | Brown-out Reset disabled. |
| BOR = ON | 0xFF | Brown-out Reset enabled. |
BORV -- Brown-out Reset Voltage bits
| BORV = 45 | 0xF3 | VBOR set to 4.5V. |
| BORV = 42 | 0xF7 | VBOR set to 4.2V. |
| BORV = 27 | 0xFB | VBOR set to 2.7V. |
CONFIG2H (address:0x300003, mask:0x1F)
WDT -- Watchdog Timer Enable bit
| WDT = OFF | 0xFE | WDT disabled (control is placed on the SWDTEN bit). |
| WDT = ON | 0xFF | WDT enabled. |
WDTPS -- Watchdog Timer Postscale Select bits
| WDTPS = 1 | 0xE1 | 1:1. |
| WDTPS = 2 | 0xE3 | 1:2. |
| WDTPS = 4 | 0xE5 | 1:4. |
| WDTPS = 8 | 0xE7 | 1:8. |
| WDTPS = 16 | 0xE9 | 1:16. |
| WDTPS = 32 | 0xEB | 1:32. |
| WDTPS = 64 | 0xED | 1:64. |
| WDTPS = 128 | 0xEF | 1:128. |
| WDTPS = 256 | 0xF1 | 1:256. |
| WDTPS = 512 | 0xF3 | 1:512. |
| WDTPS = 1024 | 0xF5 | 1:1024. |
| WDTPS = 2048 | 0xF7 | 1:2048. |
| WDTPS = 4096 | 0xF9 | 1:4096. |
| WDTPS = 8192 | 0xFB | 1:8192. |
| WDTPS = 16384 | 0xFD | 1:16384. |
| WDTPS = 32768 | 0xFF | 1:32768. |
CONFIG3H (address:0x300005, mask:0x80)
MCLRE -- MCLR Pin Enable bit
| MCLRE = OFF | 0x7F | RA5 input pin enabled, MCLR disabled. |
| MCLRE = ON | 0xFF | MCLR pin enabled, RA5 input pin disabled. |
CONFIG4L (address:0x300006, mask:0x85)
STVR -- Stack Full/Underflow Reset Enable bit
| STVR = OFF | 0xFE | Stack full/underflow will not cause Reset. |
| STVR = ON | 0xFF | Stack full/underflow will cause Reset. |
LVP -- Low-Voltage ICSP Enable bit
| LVP = OFF | 0xFB | Low-Voltage ICSP disabled. |
| LVP = ON | 0xFF | Low-Voltage ICSP enabled. |
DEBUG -- Background Debugger Enable bit
| DEBUG = ON | 0x7F | Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug. |
| DEBUG = OFF | 0xFF | Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins. |
CONFIG5L (address:0x300008, mask:0x03)
CP0 -- Code Protection bit
| CP0 = ON | 0xFE | Block 0 (00200-000FFFh) code-protected. |
| CP0 = OFF | 0xFF | Block 0 (00200-000FFFh) not code-protected. |
CP1 -- Code Protection bit
| CP1 = ON | 0xFD | Block 1 (001000-001FFFh) code-protected. |
| CP1 = OFF | 0xFF | Block 1 (001000-001FFFh) not code-protected. |
CONFIG5H (address:0x300009, mask:0xC0)
CPB -- Boot Block Code Protection bit
| CPB = ON | 0xBF | Boot Block (000000-0001FFh) code-protected. |
| CPB = OFF | 0xFF | Boot Block (000000-0001FFh) not code-protected. |
CPD -- Data EEPROM Code Protection bit
| CPD = ON | 0x7F | Data EEPROM code-protected. |
| CPD = OFF | 0xFF | Data EEPROM not code-protected. |
CONFIG6L (address:0x30000A, mask:0x03)
WRT0 -- Write Protection bit
| WRT0 = ON | 0xFE | Block 0 (00200-000FFFh) write-protected. |
| WRT0 = OFF | 0xFF | Block 0 (00200-000FFFh) not write-protected. |
WRT1 -- Write Protection bit
| WRT1 = ON | 0xFD | Block 1 (001000-001FFFh) write-protected. |
| WRT1 = OFF | 0xFF | Block 1 (001000-001FFFh) not write-protected. |
CONFIG6H (address:0x30000B, mask:0xE0)
WRTC -- Configuration Register Write Protection bit
| WRTC = ON | 0xDF | Configuration registers (300000-3000FFh) write-protected. |
| WRTC = OFF | 0xFF | Configuration registers (300000-3000FFh) not write-protected. |
WRTB -- Boot Block Write Protection bit
| WRTB = ON | 0xBF | Boot Block (000000-0001FFh) write-protected. |
| WRTB = OFF | 0xFF | Boot Block (000000-0001FFh) not write-protected. |
WRTD -- Data EEPROM Write Protection bit
| WRTD = ON | 0x7F | Data EEPROM write-protected. |
| WRTD = OFF | 0xFF | Data EEPROM not write-protected. |
CONFIG7L (address:0x30000C, mask:0x03)
EBTR0 -- Table Read Protection bit
| EBTR0 = ON | 0xFE | Block 0 (00200-000FFFh) protected from table reads executed in other blocks. |
| EBTR0 = OFF | 0xFF | Block 0 (00200-000FFFh) not protected from table reads executed in other blocks. |
EBTR1 -- Table Read Protection bit
| EBTR1 = ON | 0xFD | Block 1 (001000-001FFFh) protected from table reads executed in other blocks. |
| EBTR1 = OFF | 0xFF | Block 1 (001000-001FFFh) not protected from table reads executed in other blocks. |
CONFIG7H (address:0x30000D, mask:0x40)
EBTRB -- Boot Block Table Read Protection bit
| EBTRB = ON | 0xBF | Boot Block (000000-0001FFh) protected from table reads executed in other blocks. |
| EBTRB = OFF | 0xFF | Boot Block (000000-0001FFh) not protected from table reads executed in other blocks. |

This page generated automatically by the device-help.pl program (2012-12-22 23:51:00 UTC) from the 8bit_device.info file (rev: 1.10) of mpasmx and from the gputils source package (rev: svn 918). The mpasmx is included in the MPLAB X.