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- Features
- Configuration Bits
- RAM map
- SFR map

PIC18LF25K80
CONFIG1L (address:0x300000, mask:0x5D)
RETEN -- VREG Sleep Enable bit
| RETEN = ON | 0xFE | Ultra low-power regulator is Enabled (Controlled by SRETEN bit). |
| RETEN = OFF | 0xFF | Ultra low-power regulator is Disabled (Controlled by REGSLP bit). |
INTOSCSEL -- LF-INTOSC Low-power Enable bit
| INTOSCSEL = LOW | 0xFB | LF-INTOSC in Low-power mode during Sleep. |
| INTOSCSEL = HIGH | 0xFF | LF-INTOSC in High-power mode during Sleep. |
SOSCSEL -- SOSC Power Selection and mode Configuration bits
| SOSCSEL = LOW | 0xEF | Low Power SOSC circuit selected. |
| SOSCSEL = DIG | 0xF7 | Digital (SCLKI) mode. |
| SOSCSEL = HIGH | 0xFF | High Power SOSC circuit selected. |
XINST -- Extended Instruction Set
| XINST = OFF | 0xBF | Disabled. |
| XINST = ON | 0xFF | Enabled. |
CONFIG1H (address:0x300001, mask:0x08)
FOSC -- Oscillator
| FOSC = LP | 0xF0 | LP oscillator. |
| FOSC = XT | 0xF1 | XT oscillator. |
| FOSC = HS2 | 0xF2 | HS oscillator (High power, 16 MHz - 25 MHz). |
| FOSC = HS1 | 0xF3 | HS oscillator (Medium power, 4 MHz - 16 MHz). |
| FOSC = EC3IO | 0xF4 | EC oscillator, CLKOUT function on OSC2 (High power, 16 MHz - 64 MHz). |
| FOSC = EC3 | 0xF5 | EC oscillator (High power, 16 MHz - 64 MHz). |
| FOSC = RC | 0xF6 | External RC oscillator, CLKOUT function on OSC2. |
| FOSC = RCIO | 0xF7 | External RC oscillator. |
| FOSC = INTIO2 | 0xF8 | Internal RC oscillator. |
| FOSC = INTIO1 | 0xF9 | Internal RC oscillator, CLKOUT function on OSC2. |
| FOSC = EC2IO | 0xFA | EC oscillator, CLKOUT function on OSC2 (Medium power, 160 kHz - 16 MHz). |
| FOSC = EC2 | 0xFB | EC oscillator (Medium power, 160 kHz - 16 MHz). |
| FOSC = EC1IO | 0xFC | EC oscillator, CLKOUT function on OSC2 (Low power, DC - 160 kHz). |
| FOSC = EC1 | 0xFD | EC oscillator (Low power, DC - 160 kHz). |
PLLCFG -- PLL x4 Enable bit
| PLLCFG = OFF | 0xEF | Disabled. |
| PLLCFG = ON | 0xFF | Enabled. |
FCMEN -- Fail-Safe Clock Monitor
| FCMEN = OFF | 0xBF | Disabled. |
| FCMEN = ON | 0xFF | Enabled. |
IESO -- Internal External Oscillator Switch Over Mode
| IESO = OFF | 0x7F | Disabled. |
| IESO = ON | 0xFF | Enabled. |
CONFIG2L (address:0x300002, mask:0x7F)
PWRTEN -- Power Up Timer
| PWRTEN = ON | 0xFE | Enabled. |
| PWRTEN = OFF | 0xFF | Disabled. |
BOREN -- Brown Out Detect
| BOREN = OFF | 0xF9 | Disabled in hardware, SBOREN disabled. |
| BOREN = ON | 0xFB | Controlled with SBOREN bit. |
| BOREN = NOSLP | 0xFD | Enabled while active, disabled in SLEEP, SBOREN disabled. |
| BOREN = SBORDIS | 0xFF | Enabled in hardware, SBOREN disabled. |
BORV -- Brown-out Reset Voltage bits
| BORV = 0 | 0xE7 | 3.0V. |
| BORV = 1 | 0xEF | 2.7V. |
| BORV = 2 | 0xF7 | 2.0V. |
| BORV = 3 | 0xFF | 1.8V. |
BORPWR -- BORMV Power level
| BORPWR = LOW | 0x9F | BORMV set to low power level. |
| BORPWR = MEDIUM | 0xBF | BORMV set to medium power level. |
| BORPWR = HIGH | 0xDF | BORMV set to high power level. |
| BORPWR = ZPBORMV | 0xFF | ZPBORMV instead of BORMV is selected. |
CONFIG2H (address:0x300003, mask:0x7F)
WDTEN -- Watchdog Timer
| WDTEN = OFF | 0xFC | WDT disabled in hardware; SWDTEN bit disabled. |
| WDTEN = NOSLP | 0xFD | WDT enabled only while device is active and disabled in Sleep mode; SWDTEN bit disabled. |
| WDTEN = ON | 0xFE | WDT controlled by SWDTEN bit setting. |
| WDTEN = SWDTDIS | 0xFF | WDT enabled in hardware; SWDTEN bit disabled. |
WDTPS -- Watchdog Postscaler
| WDTPS = 1 | 0x83 | 1:1. |
| WDTPS = 2 | 0x87 | 1:2. |
| WDTPS = 4 | 0x8B | 1:4. |
| WDTPS = 8 | 0x8F | 1:8. |
| WDTPS = 16 | 0x93 | 1:16. |
| WDTPS = 32 | 0x97 | 1:32. |
| WDTPS = 64 | 0x9B | 1:64. |
| WDTPS = 128 | 0x9F | 1:128. |
| WDTPS = 256 | 0xA3 | 1:256. |
| WDTPS = 512 | 0xA7 | 1:512. |
| WDTPS = 1024 | 0xAB | 1:1024. |
| WDTPS = 2048 | 0xAF | 1:2048. |
| WDTPS = 4096 | 0xB3 | 1:4096. |
| WDTPS = 8192 | 0xB7 | 1:8192. |
| WDTPS = 16384 | 0xBB | 1:16384. |
| WDTPS = 32768 | 0xBF | 1:32768. |
| WDTPS = 65536 | 0xC3 | 1:65536. |
| WDTPS = 131072 | 0xC7 | 1:131072. |
| WDTPS = 262144 | 0xCB | 1:262144. |
| WDTPS = 524288 | 0xCF | 1:524288. |
| WDTPS = 1048576 | 0xFF | 1:1048576. |
CONFIG3H (address:0x300005, mask:0x89)
CANMX -- ECAN Mux bit
| CANMX = PORTC | 0xFE | ECAN TX and RX pins are located on RC6 and RC7, respectively. |
| CANMX = PORTB | 0xFF | ECAN TX and RX pins are located on RB2 and RB3, respectively. |
MSSPMSK -- MSSP address masking
| MSSPMSK = MSK5 | 0xF7 | 5 bit address masking mode. |
| MSSPMSK = MSK7 | 0xFF | 7 Bit address masking mode. |
MCLRE -- Master Clear Enable
| MCLRE = OFF | 0x7F | MCLR Disabled, RG5 Enabled. |
| MCLRE = ON | 0xFF | MCLR Enabled, RE3 Disabled. |
CONFIG4L (address:0x300006, mask:0x91)
STVREN -- Stack Overflow Reset
| STVREN = OFF | 0xFE | Disabled. |
| STVREN = ON | 0xFF | Enabled. |
BBSIZ -- Boot Block Size
| BBSIZ = BB1K | 0xEF | 1K word Boot Block size. |
| BBSIZ = BB2K | 0xFF | 2K word Boot Block size. |
CONFIG5L (address:0x300008, mask:0x0F)
CP0 -- Code Protect 00800-01FFF
| CP0 = ON | 0xFE | Enabled. |
| CP0 = OFF | 0xFF | Disabled. |
CP1 -- Code Protect 02000-03FFF
| CP1 = ON | 0xFD | Enabled. |
| CP1 = OFF | 0xFF | Disabled. |
CP2 -- Code Protect 04000-05FFF
| CP2 = ON | 0xFB | Enabled. |
| CP2 = OFF | 0xFF | Disabled. |
CP3 -- Code Protect 06000-07FFF
| CP3 = ON | 0xF7 | Enabled. |
| CP3 = OFF | 0xFF | Disabled. |
CONFIG5H (address:0x300009, mask:0xC0)
CPB -- Code Protect Boot
| CPB = ON | 0xBF | Enabled. |
| CPB = OFF | 0xFF | Disabled. |
CPD -- Data EE Read Protect
| CPD = ON | 0x7F | Enabled. |
| CPD = OFF | 0xFF | Disabled. |
CONFIG6L (address:0x30000A, mask:0x0F)
WRT0 -- Table Write Protect 00800-03FFF
| WRT0 = ON | 0xFE | Enabled. |
| WRT0 = OFF | 0xFF | Disabled. |
WRT1 -- Table Write Protect 04000-07FFF
| WRT1 = ON | 0xFD | Enabled. |
| WRT1 = OFF | 0xFF | Disabled. |
WRT2 -- Table Write Protect 08000-0BFFF
| WRT2 = ON | 0xFB | Enabled. |
| WRT2 = OFF | 0xFF | Disabled. |
WRT3 -- Table Write Protect 0C000-0FFFF
| WRT3 = ON | 0xF7 | Enabled. |
| WRT3 = OFF | 0xFF | Disabled. |
CONFIG6H (address:0x30000B, mask:0xE0)
WRTC -- Config. Write Protect
| WRTC = ON | 0xDF | Enabled. |
| WRTC = OFF | 0xFF | Disabled. |
WRTB -- Table Write Protect Boot
| WRTB = ON | 0xBF | Enabled. |
| WRTB = OFF | 0xFF | Disabled. |
WRTD -- Data EE Write Protect
| WRTD = ON | 0x7F | Enabled. |
| WRTD = OFF | 0xFF | Disabled. |
CONFIG7L (address:0x30000C, mask:0x0F)
EBTR0 -- Table Read Protect 00800-03FFF
| EBTR0 = ON | 0xFE | Enabled. |
| EBTR0 = OFF | 0xFF | Disabled. |
EBTR1 -- Table Read Protect 04000-07FFF
| EBTR1 = ON | 0xFD | Enabled. |
| EBTR1 = OFF | 0xFF | Disabled. |
EBTR2 -- Table Read Protect 08000-0BFFF
| EBTR2 = ON | 0xFB | Enabled. |
| EBTR2 = OFF | 0xFF | Disabled. |
EBTR3 -- Table Read Protect 0C000-0FFFF
| EBTR3 = ON | 0xF7 | Enabled. |
| EBTR3 = OFF | 0xFF | Disabled. |
CONFIG7H (address:0x30000D, mask:0x40)
EBTRB -- Table Read Protect Boot
| EBTRB = ON | 0xBF | Enabled. |
| EBTRB = OFF | 0xFF | Disabled. |

This page generated automatically by the device-help.pl program (2012-12-22 23:51:01 UTC) from the 8bit_device.info file (rev: 1.10) of mpasmx and from the gputils source package (rev: svn 918). The mpasmx is included in the MPLAB X.